Fundamentals of VLSI Design using Verilog and Cadence (In-Campus Mode)
Start Date & Time15-Jun-202610:00 AM - 12:00 PM
Duration04 Weeks / 45 hour(s)
Course Fees2250/-
EligibilityAnyone interested in VLSI Design with basic knowledge of Digital Logics and Circuits.
Course Coordinator(s)
- Sh. Arjesh Jha
Mb: 9560513251
